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AR# 14252

4.1i XST - "ERROR:Xst:935 - <file>.v Line xx. Block 'name' previously declared"

Description

Keywords: XST, 935, block, declared, name, Verilog

Urgency: Standard

General Description:
When I compile a Verilog design with XST, the following error occurs:

"ERROR:Xst:935 - <file>.v Line xx. Block 'name' previously declared."

Solution

Sequential statements can be named with identifiers in Verilog, but the names must be unique. Statements cannot be given the same name as signals used, instance names, or the module itself.

In the following example, "top" is an illegal name to use:

<code>
module top (CLK, DIN, DOUT);
input CLK, DIN;
output DOUT;
reg DOUT;

always @(posedge CLK) begin : DOUT // The process can be named here, but the name must be unique.
DOUT = DIN;
end

endmodule
</code>
AR# 14252
Date Created 03/20/2002
Last Updated 08/06/2003
Status Archive
Type General Article