UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 14269

4.1i XST - "WARNING:Xst:1067 - <file>.v Line xx. Port sizes don't match in port #N"

Description

Keywords: XST, 1067, port, size, Verilog, instantiate, module

Urgency: Standard

General Description:
When I synthesize a Verilog design in XST, the following warning occurs during parsing:

"WARNING:Xst:1067 - <file>.v Line xx. Port sizes don't match in port #N."

Solution

XST has determined that the size of a bus connected to a port of a sub-module does not match the declared port size within that sub-module. The value of N will point out which port has the discrepancy.

Confirm that the sizes of the signals connected to a sub module match the declarations within that sub-module to ensure proper assembly of the hierarchy.
AR# 14269
Date Created 03/21/2002
Last Updated 08/06/2003
Status Archive
Type General Article