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AR# 14270

XST - "ERROR:Xst:880 - "file.v", line xx: Cannot mix blocking and non-blocking assignments on signal <sig>"


Keywords: Verilog, synthesis, synthesize, analysis, analyze

Urgency: Standard

General Description:
When I synthesize a Verilog design in XST, the following warning occurs during analysis:

"ERROR:Xst:880 - "file.v", line xx: Cannot mix blocking and non-blocking assignments on signal <sig>."



XST rejects Verilog designs if a given signal is assigned through both blocking and non-blocking assignments. For example:

always @(in1) begin
if (in2) out1 = in1;
else out1 <= in2;

If a variable is assigned in both a blocking and non-blocking assignment, the above error message is reported.

Restrictions also exist when blocking and non-blocking assignments are mixed on bits and slices. The following example will be rejected, even if there is no genuine mixing of blocking and non-blocking assignments:

if (in2) begin
out1[0] = 1'b0;
out1[1] <= in1;
else begin
out1[0] = in2;
out1[1] <= 1'b1;

Errors are checked at the signal level, not at the bit level. If there is more than a single blocking/non-blocking error, only the first one will be reported. In some cases, the line number for the error might be incorrect (as there might be multiple lines in which the signal has been assigned).
AR# 14270
Date 10/20/2005
Status Active
Type General Article