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AR# 14272

6.1i HDL Bencher - Subtypes contained within packages are assigned incorrect vector sizes in HDL Bencher

Description

Keywords: HDL Bencher, subtypes, VHDL, 4.2i, testbench

Urgency: Hot

General Description:
When I use subtypes within my VHDL code, HDL Bencher incorrectly identifies these and transfers them to a testbench that has a conflicting value.

For example:

constant cCntWidth : integer := 4;
subtype stCntVec is std_logic_vector(cCntWidth-1 downto 0);

HDL Bencher then assigns stCntVec to:

COMPONENT MyPackCnt
PORT (
Reset : in std_logic;
Clock : in std_logic;
OutPulse : out std_logic;
OutPulse2nd : out std_logic;
TstOut : out stCntVec (31 DOWNTO 0)
);
END COMPONENT;

SIGNAL Reset : std_logic;
SIGNAL Clock : std_logic;
SIGNAL OutPulse : std_logic;
SIGNAL OutPulse2nd : std_logic;
SIGNAL TstOut : stCntVec (31 DOWNTO 0);

This causes the following error in ModelSim:

"# WARNING[1]: mypackcnt_tb.vhw(57): Entity port length is 4. tstout length is 32."
"# ERROR: mypackcnt_tb.vhw(127): Index constraint cannot be applied to constrained type."

Solution

To work around this issue, manually edit the "*.vhw" file (i.e., "designname_tb.vhw") that is generated by HDL Bencher, removing the vector size from the testbench as follows:

COMPONENT MyPackCnt
PORT (
Reset : in std_logic;
Clock : in std_logic;
OutPulse : out std_logic;
OutPulse2nd : out std_logic;
TstOut : out stCntVec
);
END COMPONENT;

SIGNAL Reset : std_logic;
SIGNAL Clock : std_logic;
SIGNAL OutPulse : std_logic;
SIGNAL OutPulse2nd : std_logic;
SIGNAL TstOut : stCntVec;
AR# 14272
Date Created 03/22/2002
Last Updated 03/19/2006
Status Archive
Type General Article