UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 14280

XST - "WARNING:Xst:863 - ".v", line xx: Name conflict ( and , renaming name as name_rnm0)"

Description

General Description:

When I synthesize a Verilog design in XST, the following warning appears:

"WARNING:Xst:863 - "<file>.v", line xx: Name conflict (<name> and <NAME>, renaming name as name_rnm0)."

Why?

Solution

Although Verilog is case-sensitive, any tools that run after synthesis may not be. To avoid potential contention at a later time, XST renames signals during analysis. The first instance name remains, but any subsequent instances are given an "_rnm#" suffix, where "#" is an index beginning with 0 (and increasing as more instances are found).

To avoid this warning and subsequent renaming, be sure to give all your signals unique names that differ by more than capitalization.

AR# 14280
Date Created 08/29/2007
Last Updated 12/15/2012
Status Active
Type General Article