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AR# 14301

XST - "ERROR:HDLParsers:1402 - filename.vhd Line xx. Object <port> of mode IN cannot be updated."

Description

Keywords: input, type, direction, process, VHDL, Verilog, synthesis

Urgency: Standard

General Description:
If an input port in a design is assigned a value in a process/always block, the following error message is reported:

"ERROR:HDLParsers:1402 - filename Line xx. Object <port> of mode IN cannot be updated."

Solution

Input ports in synthesis tools cannot be updated inside a process/always block. If the port needs to be updated, you must drive the port onto a signal in the process/always block.

For example:

For VHDL:

process (clock) is begin
if clock'event and clock = '1' then
d_port <= signal_name;
end if;
end process;

NOTE: "d_port" is a port on the VHDL component that is being updated. This is an error.

Change the above example to:

process (clock) is begin
if clock'event and clock = '1' then
d_signal <= d_port;
end if;
end process;

NOTE: "d_signal" is not a port in this case; however, it is being updated by "d_port," which is a port.

For Verilog:

always @(posedge clock) begin
d_port <= signal_name;
end;

NOTE: "d_port" is a port on the Verilog module that is being updated. This is an error.

Change the above example to:

always @(posedge clock) begin
d_signal <= d_port;
end;

NOTE: "d_signal" is not a port in this case; however, it is being updated by "d_port," which is a port.
AR# 14301
Date Created 08/29/2007
Last Updated 10/20/2005
Status Active
Type General Article