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AR# 14303

4.1i XST - "ERROR:Xst:945 - file.v Line xx. Input port 'port_name' cannot be redefined as a REG"

Description

Keywords: Verilog, data, type, reg, integer, time

Urgency: Standard

General Description:
If an input port is declared as a "reg", "integer", or "time" data type (all of which are considered to be "reg" data types), XST reports the following error:

"ERROR:Xst:945 - file.v Line xx. Input port 'port_name' cannot be redefined as a REG."

Solution

Verilog only supports the data types "wire" and "tri" for synthesis. To avoid this error, go to the line number listed in the error message and declare the port as a "wire" or "tri". Removing the declaration altogether will cause the data type to default to "wire".
AR# 14303
Date Created 03/25/2002
Last Updated 08/06/2003
Status Archive
Type General Article