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AR# 14304

4.1i XST - "ERROR:Xst:943 - file.v Line xx. The name 'signal' has already been declared"


Keywords: data, type, declare, declaration, Verilog, reg, net, wire

Urgency: Standard

General Description:
If a Verilog net or reg has been declared, re-declaring it will cause the following XST error:

"ERROR:Xst:943 - file.v Line xx. The name 'signal' has already been declared."


To avoid this error, go to the line number and evaluate the declaration of the signal in question. If the declaration is correct, find the previous declaration and remove it. If the declaration is incorrect, remove it.
AR# 14304
Date Created 03/25/2002
Last Updated 08/06/2003
Status Archive
Type General Article