Keywords: VHDL, synthesize, synthesis, 8.1i, 7.1i , 9.2i, 10.1
When I synthesize a VHDL design with XST, the following warning occurs:
"WARNING:Xst:819 - <file>.vhd (Line xx). The following signals are missing in the process sensitivity list: <sig>"
Why do I receive this warning message?
Case 1:
This warning occurs if an input signal of a process block is not listed in the sensitivity list of that block.
For example:
<code>
process (clk) -- Note that "rst" is not listed here.
begin
if (rst='1') then
dout <= '0';
elsif (clk'event and clk='1') then
dout <= din;
end if;
end process;
</code>
The signal "rst" is not listed in the sensitivity list. Synthesis results are not affected by this omission, but simulation results might differ, prompting the above warning message.
Case 2:
XST generates the above warning message when a signal of record type is used in the sensitivity list. XST erroneously issues the warning for the subelements of the record type.
This issue is fixed in ISE 9.1i.