We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 1432

HARDWARE DEBUGGER: Many internal signals cannot be selected


When running the Hardware debugger, several internal signals cannot be
selected although they are present in the .lca and .xtf files


Not all siganls can be selected by hardware debugger. Only
the signal names that show up in the <design>.ll file are
available. The .ll file lists all internal nodes that
corespond to a probe point such as CLB outputs.

If the name is not on the list then there is no way to force
it to be on the list without re-implementing the design.
If you would like to Re-implement the design for this purpose,
you can force the net to be external to a CLB by placing an
X attribute on the net. This should put the net name at a
probable location and makebits will enter the proper names
into the .ll file

AR# 1432
Date Created 10/25/1996
Last Updated 11/10/2004
Status Archive
Type General Article