Select the "stepping" speed grade for the Virtex-II part, then add the following to your HDL code:
VHDL:library ieee;
library synplify;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use synplify.attributes.all;
entity mult_test is
port ( <port_list>);
attribute xc_props of mult_test : entity is "CONFIG STEPPING=1";
end entity;
:
:
Verilog:module mult_test (<port_list>) /*synthesis xc_props="CONFIG STEPPING=1"*/;
:
:
endmodule
For more information about the STEPPING attribute, please see
(Xilinx Answer 14339).