BREFCLK is an alternative routing resource for the RocketIO Transceiver's reference clock. Because of its superior jitter characteristics, Xilinx recommends that BREFCLK be used for any designs requiring an MGT to operate at > = 2.5 Gbps. Like REFCLK, it must receive a low-jitter differential clock source. Please see the RocketIO User Guide for further details.
BREFCLK is fully supported by Xilinx design tools in the 5.1i software release. Is there a way to implement it in earlier software versions?
BREFCLK can be enabled by using 4.2i Service Pack 3 with one of the following patches (see the readme.txt file within the archive for instructions).