UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 14372

8.1i XST - "ERROR:Xst:761 or ERROR:Xst:762 - .vhd Line xx: No default binding for component: . Port does not match"

Description

When I analyze a VHDL design, the following error occurs:

"ERROR:Xst:762 - <file>.vhd (Line xx). No default binding for component: <entity>. Port <name> does not match."

In the case of multiple ports, the following error occurs:

"ERROR:Xst:761 - <file>.vhd (Line xx). No default binding for component: <entity>. Ports <name1,name2> do not match."

Solution

Compare the component declaration and instantiation to the submodule that is instantiated. When this error occurs, the declaration matches the instantiation, but does not match the port declarations of the submodule.

Change either the port declarations in the declaration/instantiation pair or the submodule port declarations so that they match. This error is specific to the types of ports in the submodule.

Possible problems include:

- Incorrect port widths between the component declaration and the entity.

- Incorrect mode (in, out, inout, buffer) between the component declaration and the entity.

AR# 14372
Date Created 08/29/2007
Last Updated 12/15/2012
Status Active
Type General Article