When I analyze a VHDL design, the following error occurs:
"ERROR:Xst:762 - <file>.vhd (Line xx). No default binding for component: <entity>. Port <name> does not match."
In the case of multiple ports, the following error occurs:
"ERROR:Xst:761 - <file>.vhd (Line xx). No default binding for component: <entity>. Ports <name1,name2> do not match."
Compare the component declaration and instantiation to the submodule that is instantiated. When this error occurs, the declaration matches the instantiation, but does not match the port declarations of the submodule.
Change either the port declarations in the declaration/instantiation pair or the submodule port declarations so that they match. This error is specific to the types of ports in the submodule.
Possible problems include:
- Incorrect port widths between the component declaration and the entity.
- Incorrect mode (in, out, inout, buffer) between the component declaration and the entity.