Use of the "wait for" statement in VHDL is unsupported for synthesis in XST.
For example, given the following:
if clk'event and clk = '1' then
data_out <= data_in;
wait for 10 ns; -- not supported VHDL statement
XST reports the following error:
To avoid this problem, ensure that the VHDL code you are synthesizing is not a behavioral model; if it is not, remove the "wait for" statement.
If it is a behavioral model, then do not try to synthesize it.
XST is a synthesis tool and not a simulator.
If this code is supposed to be used for both synthesis and simulation, Xilinx recommends putting them in two different files, one for synthesis and the other for simulation.