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AR# 14385

5.1i XST - "ERROR:Pack:1110 - Unable to obey design constraints (MACRONAME=hset, RLOC=X4Y7)"


Keywords: RPM, RLOC, relational, place, macro, VHDL, generic

Urgency: Standard

General Description:
When I create an HDL design with RPMs (relationally placed macros), the following PAR error is reported after synthesis:

"ERROR:Pack:679 - Unable to obey design constraints (MACRONAME=hset, RLOC=X4Y7)"


The problem arises from the fact that the synthesis tool is flattening the design, which results in more than one primitive with the same RLOC constraint. You can solve this problem by setting the hierarchy switch so that the primitives are grouped together, giving the RLOCs a unique area in which to relate:

1. Right-click on the "Synthesize" process.
2. Select "Properties..."
3. Select "Keep Hierarchy" under the Synthesis Options tab.
AR# 14385
Date 10/20/2005
Status Archive
Type General Article