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AR# 14442

4.2i CORE Generator - Errors report duplicate declaration of ROC and TOC modules when I synthesize with cores

Description

Keywords: COREGen, ISE, Project, Navigator, DDC, SID, MAC, Interleaver, Deinterleaver, Verilog, glbl.v, GSR, TSR, ROC, TOC, duplicate, module, declarations, XST

Urgency: Standard

General Description
When the following cores from CORE Generator are used with IP Update #2 for 4.2i

DDC v1_0
MAC v2_0
SID v2_0 (Interleaver, Deinterleaver)

the following XST errors are reported during synthesis compilation if the design contains more than one COREGen module:

"ERROR:Xst:1068 - inter_blk_rec.v Line 1952. Duplicate declarations of module 'ROC'
Module <ROC> compiled."

"ERROR:Xst:1068 - inter_blk_rec.v Line 1964. Duplicate declarations of module 'TOC'
Module <TOC> compiled."

Solution

Even during synthesis, the simulation wrapper file (<my_core.v>) must be compiled; when the design contains multiple core instantiations, the compiler issues errors regarding the duplicate module declaration of ROC and TOC.

To work around this, comment out all the redundant ROC and TOC module declarations from the wrapper files. The following code (located at the bottom of each wrapper file) should be commented out from all except one wrapper file:

/*
module ROC(O);
output O;
reg o_out;
parameter WIDTH = 100;
BUF b1(O, o_out);
initial
begin
o_out = 1;
#WIDTH o_out = 0;
end
endmodule

module TOC(O);
output O;
reg o_out;
parameter WIDTH = 100;
BUF b1(O, o_out);
initial
begin
o_out = 1;
#WIDTH o_out = 0;
end
endmodule
*/
AR# 14442
Date Created 04/10/2002
Last Updated 10/08/2003
Status Archive
Type General Article