For Virtex, Virtex-E, and Virtex-II SelectMAP readback, the BUSY signal must be monitored, even when the configuration clock (CCLK) frequency during readback is below 50 MHz. Failure to monitor the BUSY signal might result in incorrect data being read back.
NOTE: The Xilinx programming software was designed to monitor this signal, so this is not a problem. This solution applies to custom SelectMAP configuration solution designs.
There is an asynchronous handshake between the external clock (CCLK) and the internal configuration clock (BUS_CLK) for SelectMAP. This makes it impossible to quote a fixed number of CCLK cycles before BUSY goes Low. You can use one of the following to solve this issue:
- Use logic that detects the BUSY pin state.
- Wait some period of time before attempting to read the data.
It takes approximately ten BUS_CLK cycles from the time the SelectMAP port receives the readback header to the time the readback buffer is full, at which time BUSY will go Low on the next CCLK positive edge. BUS_CLK typically runs at between 50 and 70 MHz. After the read header is loaded, CS is deasserted while you change WRITE to read mode. As a result, if you wait approximately 1 microsecond before asserting CS again, BUSY should go Low after the next positive CCLK edge.
NOTE: For Virtex-II, CS_B is the equivalent to CS, and RDWR_B is the equivalent to WRITE.