UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 14485

3.6 FPGA Express - Synthesizing a PCI core leads to "Internal Error: Invalid value 'PCIX' for attribute 'pmap_iostd' on '/PCIX_TOP/AD<63>'."

Description

Keywords: PCI, PCI-X, FPGA, Express, Virtex

Urgency: Standard

General Description:
When I synthesize the PCI or PCI-X core with ISE and use FPGA Express to target a Virtex-II device, internal errors are reported, but the flow completes.

The same errors occur in the stand-alone version of FPGA Express 3.6.1, but they are fatal errors and no netlist is created. One error is reported for every output or bidirectional output.

The errors are as follows:

For the PCI-X core:
"FPGA-INTERNAL-padmap-2 (89 Occurrences)"
"Internal Error: Invalid value 'PCIX' for attribute 'pmap_iostd' on '/PCIX_TOP/AD<63>'."
"Internal Error: Invalid value 'PCIX' for attribute 'pmap_iostd' on '/PCIX_TOP/AD<62>'."

For the PCI core:
"Internal Error: Invalid value 'SLOW' for attribute 'pmap_slew' on '/top-1/data_out'."
"Internal Error: Invalid value 'SLOW' for attribute 'pmap_slew' on '/top-1/data_out'."

Solution

This problem is fixed in the latest 4.2i Service Pack, available at:
http://support.xilinx.com/support/techsup/sw_updates
The first service pack containing the fix is 4.2i Service Pack 2.

Please download and install the FPGA Express version that is available with Service Pack 2.
AR# 14485
Date Created 04/15/2002
Last Updated 08/11/2003
Status Archive
Type General Article