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AR# 14503

4.2i Timing Analyzer - The Virtex-II/Pro primitives FDDRCPE and FDDRRSE are analyzed incorrectly


General Description:

When I specify a FROM/TO constraint from a synchronous element to the FDDRCPE or FDDRRSE double-data rate primitive, Timing Analyzer places both IOB flip-flops in the both rising and falling clock time groups. This causes the path reporting to be incorrect in the timing report between the falling and rising time groups.


This issue is fixed in the next major release of Timing Analyzer.

AR# 14503
Date Created 08/29/2007
Last Updated 01/18/2010
Status Archive
Type General Article