After I run TRCE with many local clocks, the hold times reported are too large to be accurate.
My design contains a large number of local clocks (over 100).
The problem occurs because TRCE is not able to correctly handle the large number of clocks in the design. When the TRCE tools analyze skew, they look for a common frequency. Because of the large number of clocks, the frequency is too high for the tool to handle.
The preferred method of working around the problem is to redesign and make better use of the FPGA resources. If you use only the global clock lines for high-frequency clocks, along with clock enables to manage the lower frequency clocks, the design will be better suited to an FPGA. This will allow your design to run faster, and you might be able to reduce the area of the chip by making the available resources work harder.
An alternate (but less preferable) way to work around this issue is to scale all the clocks down by a factor of 100. This should make the common clock frequency within the allowed range. If the hold numbers are still unrealistic, a larger factor should be used.