Solution

For ISE 9.1x and above, please refer to (Xilinx Answer 25517).

Running the Simulation with Cadence NC-Verilog - Solaris 2.6/2.7/2.8

Several files in the "$XILINX/smartmodel/sol/simulation/ncverilog" directory can help you set up and run a simulation utilizing the SWIFT interface. A description of each file follows:

setup file - A description of variables that must be set for correct simulation.

For example:

setenv XILINX <Xilinx path>
setenv CDS_INST_DIR <Cadence path>
setenv LM_LICENSE_FILE <license.dat>:$LM_LICENSE_FILE

setenv LMC_HOME $XILINX/smartmodel/sol/installed_sol
setenv LMC_CONFIG $LMC_HOME/data/solaris.lmc

setenv LD_LIBRARY_PATH $LMC_HOME/sim/pli/src:$LMC_HOME/lib/sun4Solaris.lib:$LD_LIBRARY_PATH
setenv LMC_CDS_VCONFIG $CDS_INST_DIR/tools/verilog/bin/vconfig

setenv PATH ${LMC_HOME}/bin ${CDS_INST_DIR}/tools/bin ${PATH}
setenv PATH ${XILINX}/bin/sol ${PATH}

You are responsible for changing the parameters included within "< >" to match your system configuration.

simulate file - An example NC-Verilog compilation simulation script that illustrates which files must be compiled and loaded for simulation. You can modify this file to simulate a design by including the design and testbench files appropriately.

For example:

ncverilog \
<design>.v <testbench>.v \
${XILINX}/verilog/src/glbl.v \
-y ${XILINX}/verilog/src/unisims +libext+.v \
-y ${XILINX}/verilog/src/simprims +libext+.v \
-y ${XILINX}/smartmodel/sol/wrappers/ncverilog +libext+.v \
+loadpli1=swiftpli:swift_boot +incdir+$LMC_HOME/sim/pli/src \
+access+r+w

You are responsible for changing the parameters included within "< >" to match your design files and testbench.

After you have updated each of these files, you can run the simulation.

Running the simulation with Cadence NC-Verilog - Linux

Several files in the "$XILINX/smartmodel/lin/simulation/ncverilog" directory can help you set up and run a simulation utilizing the SWIFT interface. A description of each file follows:

setup file - A description of variables that must be set for correct simulation.

For example:

setenv XILINX <Xilinx path>
setenv CDS_INST_DIR <Cadence path>
setenv LM_LICENSE_FILE <license.dat>:$LM_LICENSE_FILE

setenv LMC_HOME $XILINX/smartmodel/lin/installed_lin
setenv LMC_CONFIG $LMC_HOME/data/x86_linux.lmc

setenv LD_LIBRARY_PATH $CDS_INST_DIR/tools/lib:$LMC_HOME/sim/pli/src:$LMC_HOME/lib/x86_linux.lib:$LD_LIBRARY_PATH
setenv LMC_CDS_VCONFIG $CDS_INST_DIR/tools/verilog/bin/vconfig

setenv PATH ${LMC_HOME}/bin ${CDS_INST_DIR}/tools/bin ${PATH}
setenv PATH ${XILINX}/bin/lin ${PATH}

You are responsible for changing the parameters included within "< >" to match your system configuration.

simulate file - An example NC-Verilog compilation simulation script that illustrates which files must be compiled and loaded for simulation. You can modify this file to simulate a design by including the design and testbench files appropriately.

For example:

ncverilog \
<design>.v <testbench>.v \
${XILINX}/verilog/src/glbl.v \
-y ${XILINX}/verilog/src/unisims +libext+.v \
-y ${XILINX}/verilog/src/simprims +libext+.v \
-y ${XILINX}/smartmodel/lin/wrappers/ncverilog +libext+.v \
+loadpli1=swiftpli:swift_boot +incdir+$LMC_HOME/sim/pli/src \
+access+r+w

Running the simulation with Cadence NC-Verilog - Windows 2000/XP

Several files in the "%XILINX%/smartmodel/nt/simulation/ncverilog" directory can help you set up and run a simulation utilizing the SWIFT interface. A description of each file follows:

setup file - A description of variables that must be set for correct simulation.

For example:

set XILINX = <Xilinx path>
set CDS_INST_DIR = <Cadence path>
set LM_LICENSE_FILE = <license.dat>;%LM_LICENSE_FILE%

set LMC_HOME = %XILINX%\smartmodel\nt\installed_nt
set LMC_CONFIG = %LMC_HOME%\data\pcnt.lmc

set PATH = %LMC_HOME%\bin;%CDS_INST_DIR%\tools\lib;%LMC_HOME%\sim\pli\src;%LMC_HOME%\lib\pcnt.lib;%PATH%

You are responsible for changing the parameters included within "< >" to match your system configuration.

simulate file - An example NC-Verilog compilation simulation script that illustrates which files must be compiled and loaded for simulation. You can modify this file to simulate a design by including the design and testbench files appropriately.

For example:

ncverilog \
<design.v> <testbench.v> \
%XILINX%\verilog\src\glbl.v \
-y %XILINX%\verilog\src\unisims +libext+.v \
-y %XILINX%\verilog\src\simprims +libext+.v \
-y %XILINX%\smartmodel\nt\wrappers\ncverilog +libext+.v \
+access+rw \
+loadpli1=swiftpli:swift_boot +incdir+%LMC_HOME%\sim\pli\src

You are responsible for changing the parameters included within "< >" to match your design files and testbench.

After you have updated each of these files, you can run the simulation.

These environment variables and settings can be set globally, as well. Setting globally should be done in the System Environment Variables and not in the User Environment Variables.