When the PROG pin is toggled during the configuration of a Virtex-II device, the DONE pin still goes High at the end of configuration; however, the device is not correctly programmed.
Under normal circumstances, the following events occur during Virtex-II JTAG configuration:
- The synchronization word is sent to the device.
- The Startup clock is set to "JTAG clock".
- The CRC register is reset, then maintains a running CRC value.
- Configuration information is sent to the device.
- The running CRC value in the device is compared against the CRC value in the bit stream.
- If no CRC error is detected, the JSTART command is sent to the JTAG Instruction Register.
- The startup sequence is clocked by TCK.
For complete details on this process, please refer to the "JTAG / Boundary Scan Programming Mode" section in the Configuration Chapter of the Virtex-II or Virtex-II Pro User Guide:
Virtex-II Platform FPGA User Guide
Virtex-II Pro and Virtex-II Pro X FPGA User Guide
Asserting PROG on a Virtex-II device during configuration causes the following:
- The startup clock setting is reset to its default value (JTAGCLK).
- A loss of synchronization between the configuration logic and the bit stream occurs.
A loss of synchronization means that the device does not recognize any further configuration data. No portion of the device is configured, no CRC check is performed, and a CRC error is not detected.
When the JTAG JSTART command is sent to the (still unconfigured) device, the device enters the startup sequence, and DONE goes High.
- Virtex and Virtex-II FPGA synchronization: (Xilinx Answer 7891)
- Virtex FPGA startup sequence: (Xilinx Answer 8240) (This also pertains to Virtex-II.)
- Effect of the PROG pin on the Virtex-II FPGA TAP: (Xilinx Answer 11508)