UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 14743

5.1i, Virtex-II/PRO, DCM - What is the DESKEW_ADJUST attribute? (SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS)

Description

General Description:

Beginning in 4.2i Service Pack 3, a "DESKEW_ADJUST" attribute is available for DCM. How do I set this and how does this affect the DCM?

Solution

Example Syntax:

VHDL:

attribute DESKEW_ADJUST : string;

attribute DESKEW_ADJUST of DCM_INST : label is "SYSTEM_SYNCHRONOUS";

Verilog:

// synthesis attribute DESKEW_ADJUST of DCM_INST is

"SOURCE_SYNCHRONOUS"

For Synplicity:

// synthesis xc_props="DESKEW_ADJUST = SOURCE_SYNCHRONOUS;

UCF/NCF:

NOTE: The UCF/NCF flow is not supported in 4.2i Service Pack 3, but it is supported as of the ISE 5.1i software.

The UCF/NCF syntax is as follows:

INST "foo/bar" DESKEW_ADJUST= SYSTEM_SYNCHRONOUS;

The "DESKEW_ADJUST" attribute sets configuration bits that affect the clock delay alignment between the DCM output clocks and the FPGA's clock input pin. The attribute value should be selected based solely on the type of clocking arrangement used your design, which will commonly be either SOURCE_SYNCHRONOUS or SYSTEM_SYNCHRONOUS (the defaults).

NOTE: This attribute should not be used to phase-shift DCM clock outputs. Phase shifting must be performed using the DCM attributes "CLKOUT_PHASE_SHIFT" and "PHASE_SHIFT".

AR# 14743
Date Created 08/29/2007
Last Updated 12/15/2012
Status Active
Type General Article