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AR# 14762

SYNPLIFY - Synplify changes the default LVTTL OBUF from a slow slew rate to a fast slew rate

Description

General Description: 

When a timing-constrained design is synthesized through Synplify, Synplify changes the default OBUF primitives to faster versions in order to make the design meet timing. This can cause board issues for designers who are unaware that the changes took place.

Solution

To override the default behavior, set the "xc_auto_fast" attribute in the HDL code as follows: 

 

VHDL: 

 

architecture beh of top is 

attribute xc_fast_auto : boolean; 

attribute xc_fast_auto of beh : architecture is false; 

 

 

Verilog: 

 

module top (q, d, addr, we, clk) /*synthesis xc_fast_auto=0 */;

AR# 14762
Date Created 08/29/2007
Last Updated 05/14/2014
Status Archive
Type General Article