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AR# 14798

5.1i CORE Generator - When I compile XilinxCoreLib simulation models, an incorrect analyze order file is created (Issues with the "get_models" tool)

Description


General Description

When I compile XilinxCoreLib simulation models, I encounter problems regarding undefined modules. (This occurs when the "get_models" tool is run with the 5.1i software.)



In 5.1i CORE Generator, the "get_models" tool has a problem with generating the correct analyze order file when the word "USE" is preceded by "--". The "--" is often used in VHDL to indicate comment line; for example, cam_v3_0.vhd has following lines:



--Use std_logic_vector_2_int, two_comp, int_2_std_logic_vector, rat, and

-- std_logic_vector_2_posint from iputils_conv

USE XilinxCoreLib.iputils_conv.ALL;



This file will cause the analyze order file to be incorrect, and no error messages will be reported.

Solution


Generally, use of the "get_models" tools is not necessary, as all simulation models have been pre-extracted into <Xilinx>/verilog/src/xilinxcorelib and<Xilinx>/vhdl/src/xilinxcorelib, along with correct analyze order files.



The use of "get_models" may be necessary when you have installed special IP cores that have simulation models and you wish to copy them into the XilinxCoreLib directory along with the other XilinxCoreLib models. The "get_models" tool will extract all simulation models from the Xilinx/coregen/ip/... tree into the specified directory, and it will generate a new analyze_order file that will indicate the correct file compilation order. (Please see the "Get_Models" section of the CORE Generator User Guide for more information.)



Please refrain from using the "get_models" tool until the first IP Update for 5.1i becomes available. If you must run "get_models" before this release, please use the original vhdl_analyze_order file and add your new models at the end of the vhdl_analyze_order file.
AR# 14798
Date Created 08/29/2007
Last Updated 07/28/2010
Status Archive
Type General Article