We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 14857

5.1i CORE Generator - Known Issues for CORE Generator in the 5.1i software release


Keywords: COREGen, Known, Issues, 5.1i

Urgency: Standard

General Description:
This Answer Record contains a list of known issues for CORE Generator 5.1i.



Software Compatibility

Acrobat Reader Requirement
1. To view core data sheets, you must have Acrobat Reader Version 4 or later installed. You can download the latest Acrobat software from the following Adobe site:

Windows 2000
1. If you use a Windows 2000 platform, Xilinx recommends that you use the "High Color" setting for your display.
Please see (Xilinx Answer 12372).

1. Clicking on the Web Browser button does not open Netscape on Solaris and the following message is reported:
"Netscape: Couldn't find our resources?"
Please see (Xilinx Answer 11771).

2. CORE Generator does not work with Netscape 4.72 when it is launched from Project Navigator on Solaris.
Please see (Xilinx Answer 14793).

Xilinx Implementation Software Issues
When a design is imported from 3.1i, "port mismatch " and "unconnected ports" messages are reported during simulation and implementation.
Please see (Xilinx Answer 13062).

Updates Installer Tool
The Updates Installer Tool has been disabled for the remainder of the 5.x release. A problem found late in the 5.2i release allowed the installation of IP Updates incompatible with the installed Xilinx software version.

For information on the latest available CORE Generator IP Updates, refer to the Xilinx Software Updates and follow the instructions for downloading and installing these updates manually:

1. The Update Installer Tool cannot be used to install cores that have been captured by the IP Capture Tool.
Please see (Xilinx Answer 14183).

2. The installer may take several hours, or the process seems to hang.
Please see (Xilinx Answer 12544).

Memory Editor Tool
Why does the Memory Editor fail to set the last address when it creates a COE file?
Please see (Xilinx Answer 15002).

IP Capture Tool
The following error is reported when I use the IP Capture tool:
"ERROR: Cannot open file <./XilinxCoreLib/vhdl_analyze_order> for writing. No analyze order list will be generated."
Please see (Xilinx Answer 14850).

Other Known Issues
1. Using a COE to generate block memory causes the following error to be reported:
"ERROR: Improperly formatted file C:\customer\test_eip1\dpr_core.coe..."
Please see (Xilinx Answer 13102).

2. An "Update Project" box appears when I open a project with multiple repositories.
Please see (Xilinx Answer 12345).

3. The analyze order file is incorrect because "get_model" does not work if the USE line is preceded by a comment "--".
Please see (Xilinx Answer 14798).

4. XST synthesis fails and reports the following error:
"ERROR: SimGenerator: Failure of Sim to implement customization parameters core decode_810".
Please see (Xilinx Answer 14684).

1. DA FIR V7_0, DDC V1_0 GUI, and MAC FIR V1_0
In the GUI, an error that reports an invalid parameter in the COE file is displayed in a different base format.
Please see (Xilinx Answer 14202).

2. MAC FIR V1_0
Incorrect results are reported for 2-tap non-symmetric and 2- or 3-tap symmetric filters.
Please see (Xilinx Answer 14242).

3. MAC FIR V1_0
After the initial load of the COE, the (COE) file can not be reloaded.
Please see (Xilinx Answer 14323).

4. DDS V4_1
When the Xilinx Implementation tool is run with DDS v4.1, the following error is reported:
"ERROR:Place:1751 - Structured logic associated with an F7 configuration could not be placed."
Please see (Xilinx Answer 14122).

1. When XilinxCoreLib files are compiled using Synopsys VSS or VCSi, simulators report a number of warnings and errors.
Please see (Xilinx Answer 12630).

2. When XilinxCoreLib files are compiled using Cadence NCVHDL, simulators report a number of warnings and errors.
Please see (Xilinx Answer 14185).

3. Pre-compiled XilinxCoreLib libraries for ModelSim Xilinx Edition II (MXE) are currently undergoing testing. Once testing has been completed, the pre-compiled libraries will be available at:
AR# 14857
Date Created 06/11/2002
Last Updated 03/05/2003
Status Archive
Type General Article