We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 14864

6.1i Virtex-II MAP - Timing tools may flag a false path through F5MUX


Keywords: timing, merge, logic corrupted, F5MUX

Urgency: Standard

General Description:
A timing problem exists that is sometimes mistaken for a mapping problem involving the corruption of logic. When an F5MUX is configured as a route-through with a constant on the select pin, MAP still uses the slice resources connected to the never-selected F5MUX input. The timing tools do not consider that the F5MUX path is never selected and flag timing violations on these false paths.

You may mistake these false paths as evidence of logic corruption. This problem is more likely to occur if the wide gate option (-k) is turned on, which makes frequent use of F5MUXs with this configuration.


This problem has been fixed in the latest 6.1i Service Pack, available at:
The first service pack containing the fix is 6.1i Service Pack 1.

You can also avoid this problem by using mapping constraints to avoid the MAP packs, or by using TIG constraints to disable these paths in the timing tools.
AR# 14864
Date Created 08/29/2007
Last Updated 03/02/2006
Status Archive
Type General Article