My design has an input FF and a 3-state FF with IOB=TRUE properties, each of which is driven by the same logical S/R signal. XST is buffering the reset signal, causing it to be logically correct but unable to be packed in the same IOB.
You can avoid this issue by placing a "max_fanout" XST directive on the reset line to prevent XST from buffering the reset signal. See the examples below for more information based on the simulation tools you are using.
This issue has been fixed in ISE 7.1i.
Please see work-arounds for older design tools below:
port (d : in std_logic;
clk : in std_logic;
rst : in std_logic;
q : out std_logic);
attribute max_fanout : string;
attribute max_fanout of rst : signal is "1000";
module flip_flop (d, clk, rst, q);
input d, clk, rst;
//synthesis attribute max_fanout rst "1000"