AR #14874 - 7.1i XST - Known Issues for designing counters

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7.1i XST - Known Issues for designing counters

AR#	14874
Topic	XST General
Last Modified	2005-10-21 00:00:00.0
Status	Active

Description

Keywords: VHDL, Verilog, limitations, prevent, infer

Urgency: Standard

General Description:
The following known limitations can prevent XST from inferring counters:

- The counter load signal is connected to a comparator.
- The counter count statement comes before the load control signal.
- The counter counts by a power of 2.
- Not all count bits are connected.
- The count statement consists of the concatenation operator and the count value.

Solution

In each situation listed above, XST produces sub-optimal timing results. The only way to work around this issue is to avoid the above conditions when inferring counters.