We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 14874

7.1i XST - Known Issues for designing counters


General Description: 

The following known limitations can prevent XST from inferring counters: 


- The counter load signal is connected to a comparator. 

- The counter count statement comes before the load control signal. 

- The counter counts by a power of 2. 

- Not all count bits are connected. 

- The count statement consists of the concatenation operator and the count value.


In each situation listed above, XST produces sub-optimal timing results. The only way to work around this issue is to avoid the above conditions when inferring counters.

AR# 14874
Date Created 08/29/2007
Last Updated 05/14/2014
Status Archive
Type General Article