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AR# 14966

5.1i XST - STARTUP_VIRTEX2 does not reset all the flip-flops in my design

Description

Keywords: XST, VIRTEX, reset, fanout, STARTUP, GSR

Urgency: Standard.

General Description:
My XST design contains an instantiated STARTUP_VIRTEX2. The reset signal is incorrectly being routed to individual flip-flops, and does not reset all the flip-flops in my design.

Solution

1

An XST synthesis tool option allows you to define the maximum fanout for a design. Setting this option will prevent the reset from routing directly to other flip-flops:

1. Right-click on the "Synthesize" process.
2. Select "Properties".
3. Select the Synthesis properties menu (under the Xilinx Specific Options tab).
4. Set "Maximum Fanout" to a high number (e.g., 10000).

2

An XST synthesis tool option allows you to define the maximum fanout for a design. Setting this option will prevent the reset from routing directly to other flip-flops:

Verilog Example:

module my_design (..., reset, ...);
:
input reset; //synthesis attribute max_fanout of reset is "10000"
:
:
endmodule

3

An XST synthesis tool option allows you to define the maximum fanout for a design. Setting this option will prevent the reset from routing directly to other flip-flops:

VHDL Example:

entity my_design is
port (
:
:
reset : in std_logic;
:
:);

attribute max_fanout : string;
attribute max_fanout of reset : signal is "10000";

end entity;
AR# 14966
Date Created 06/25/2002
Last Updated 10/20/2005
Status Archive
Type General Article