AR #15060 - Virtex-II Pro RocketIO - If I have a single REFCLK driving two or more MGTs on opposite sides of the chip, will REFCLK be routed through a BUFG to minimize skew?

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Virtex-II Pro RocketIO - If I have a single REFCLK driving two or more MGTs on opposite sides of the chip, will REFCLK be routed through a BUFG to minimize skew?

AR#	15060
Part	Part Not Listed
Last Modified	2008-05-15 00:00:00.0
Status	Active
Keywords	I/O, IO, multi, gigabit, transceiver, MGT, refclk, clock, input, multiple

Description

Keywords: I/O, IO, multi, gigabit, transceiver, MGT, refclk, clock, input, multiple

If I have a single REFCLK driving two or more MGTs on opposite sides of the chip, will REFCLK be routed through a BUFG to minimize skew?

Solution

The ideal solution in this case is to bring REFCLK in through two separate input pins. If this is not possible, a BUFG can be used to distribute a single REFCLK input throughout the chip. However, be aware that routing REFCLK through a BUFG can lead to excessive jitter.