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AR# 15090

5.1i Timing Simulation, NGDAnno - Invalid X_SUH Setup\Hold violations occur during timing simulation

Description

Keywords: timing, simulation, NGDAnno, SUH, X_SUH, GSUH, setup, hold, violation, DCM, CE, LVDS, LVPECL, DCM

Urgency: Standard

General Description:
When I perform a timing simulation, the following errors are reported:

Verilog:
"# ** Error: C:/XILINX/verilog/src/simprims/X_SUH.v(32): $setup( posedge I &&& CE:240 ns, posedge CLK:241 ns, 1800 ps );"
"# Time: 241 ns Iteration: 2 Instance: /testbench/UUT/GSUH_datain_clk."

VHDL:
"# ** Warning: */X_SUH SETUP High VIOLATION ON I WITH RESPECT TO CLK;"
"# Expected := 1.8 ns; Observed := 1 ns; At : 341 ns."
"# Time: 341 ns Iteration: 3 Instance: /testbench/uut/gsuh_datain_clk."

In many cases, these errors are invalid. The following known issues can cause invalid errors with these external setup and hold checks:

1. Using the DCM to generate a clock
The calculations are only valid when the CLK0 output of the DCM is used. The calculations cannot currently account for any phase shifting or period adjustment of the clock. As a result, the checks are invalid when any output other than CLK0 is used.
2. Using differential clocks
The checks currently look at the rising edge of both the P and the N side of the clock. This causes the check on the N side to be invalid.
3. Using bidirectional ports
These checks are only valid for inputs, but the X_SUH cell is always enabled. As a result, invalid errors may occur when the port is used as an output.
4. Using registers with an enable
The X_SUH cell has an enable input, but it is currently tied to VCC. Consequently, errors may occur on a register, even when the enable input of the register is de-asserted.

For information on how the external setup and hold checks are calculated and why they are used, please see (Xilinx Answer 6893).

Solution

1

These checks are disabled in the latest 5.1i Service Pack available at:
http://support.xilinx.com/support/techsup/sw_updates
The first service pack containing the fix is 5.1i Service Pack 2.

The checks are disabled until the issues described above are resolved. This disables the external setup and hold checks in the simulation. You should perform thorough static timing analysis on the I/Os instead.

2

If you are using a software version prior to 5.1.02i, you can disable the insertion of the X_SUH cells by using the following environment variable:

Workstation:
setenv XIL_ANNO_DISABLE_GSUH 1

PC:
set XIL_ANNO_DISABLE_GSUH=1

Once the environment variable is set, you must run NGDAnno again. In ISE, rerun the Generate Post-Place-and-Route simulation model. This disables the external setup and hold checks in the simulation. You should perform thorough static timing analysis on the I/Os instead.
AR# 15090
Date Created 07/09/2002
Last Updated 08/11/2005
Status Archive
Type General Article