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AR# 15130

Virtex-II/Virtex-II Pro DCM - To use variable phase shift, a BitGen option must be set and phase shift must be in the positive range


To obtain the best results when using DCM phase shift in variable mode, you must set a BitGen option and set the phase shift in the positive range. Xilinx strongly recommends this strategy for new designs and for existing designs that experience one of the following failure modes. For existing designs that are working in the board using the default settings, this strategy is not mandatory. In designs that fail, the failures are consistent and obvious.

NOTE: This recommendation applies to both Virtex-II and Virtex-II Pro designs.

Failure Modes

- The DCM LOCKED signal does not assert.

- The LOCKED signal asserts and the DCM functions normally. However, the clock output is in one of two phases (one correct, one incorrect), and the phase that is present might vary with subsequent resets.

- The DCM produces a clock with a bad duty cycle (e.g., 30/70).

- Some or all of the DCM clock outputs stop toggling.

NOTE: If you continue to experience this failure after following the BitGen option instructions detailed below, or experience similar failure modes with a DCM set to FIXED phase shift mode, please open a WebCase at:



BitGen Option

Beginning in software version 5.1i SP1 for Virtex-II, the BitGen "Centered_x#y#" option is available. You can set this option to :0 or :1 (the default value is :1). You must set this option to "0" when the DCM is in variable phase shift mode.

NOTE: For Virtex-II Pro, the option is available beginning with software version 5.1i SP3.

For example:

bitgen -g Centered_x0y0:0 design.ncd

This sets the DCM at site x0y0 to the proper configuration. If multiple DCMs with variable phase shift are used in your design, apply the "Centered_x#y#" option to each DCM location.

The specific BitGen "-g" options are:


Variable Phase Shift in the Positive Range

Setting the BitGen "Centered_x#y#" option allows the phase shift range of 10 ns to be retained, but only in the positive phase shift range (compared to +/- 5 ns in negative and positive range with default settings).


If PHASE_SHIFT = 0, the DCM should not be set to decrement. If it is set to decrement beyond 0 phase shift, the DCM reverses direction and increments.

If PHASE_SHIFT = 255, the DCM cannot increment.

If PHASE_SHIFT = 128, the DCM can increment up to 255 and decrement down to 0 as long as the phase shifts are within the 10 ns range.

For most cases, any negative PHASE_SHIFT value will have its equivalent positive phase shift.

Affected Reference Designs

The requirements for using variable phase shift in the positive range and setting the BitGen option affects several reference designs:

- Application Notes Whose Designs use Dynamic Phase Shift Alignment

1. An update to the "644-MHz SDR LVDS Transmitter/Receiver" Application Note (Xilinx XAPP622) is in progress, but completed design files are currently available. The "reference design" link in this Application Note reflects the updated design files at:

Please use these updated design files with the BitGen option described above.

- Designs Using an SPI 4.2 (PL4) Core

Use the SPI 4.2 (PL4) version 5.1 or later core (v5.2 is the latest as of February 3, 2003). This SPI 4.2 version uses the FIXED phase shift mode for static alignment; consequently, the BitGen "Centered_x#y#" option is not necessary. See (Xilinx Answer 16112) for information on determining the correct PHASE_SHIFT value in fixed phase shift mode.

SPI-4.2 (or PL4) Core versions 4.0 and 5.0 use DCM in variable phase shift mode regardless of whether automatic static alignment or fixed static alignment is selected. Consequently, these versions are not recommended for new designs or for designs experiencing the DCM issues mentioned in this Answer Record. If you must use one of these versions, see (Xilinx Answer 16637).

- Other Application Note Reference Designs

By default, the designs in (Xilinx XAPP265): "High-Speed Data Serialization and Deserialization (840 Mb/s LVDS)" and (Xilinx XAPP253): "Synthesizable 400 Mb/s DDR SDRAM Controller" use fixed phase shift. If you modify the designs in these Application Notes to use variable phase shift, please use the BitGen option and positive phase shift range as described above.

Linked Answer Records

Associated Answer Records

AR# 15130
Date 12/15/2012
Status Active
Type General Article
  • Virtex-II
  • Virtex-II Pro
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