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AR# 15184

2.2 System Generator for DSP - Distributed SPRAM is not using the clock enable net and is constrained to run at the fastest rate


General Description: 

In System Generator for DSP v2.2, timing groups are created through the use of clock enable nets. In my Single-Port Distributed RAM block, the core is not using the clock enable net. This means that all distributed RAMs must run at the system rate -- this problem prevents me from meeting my timing requirement.


A patch to fix this bug will be available in mid-November, 2002.  


If you require this patch before then, please contact Xilinx Customer Service by opening a WebCase at: 


AR# 15184
Date Created 09/03/2007
Last Updated 05/14/2014
Status Archive
Type General Article