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AR# 15192

LogiCORE SPI-4.2 (POS-PHY L4) v4.x - For a Sink PL4 core, the "SnkStat" input is not reflected on RStat for certain SnkStatClk phases and frequencies

Description

Keywords: PL4, sink, POS PHY, Level 4, SnkStatClk, RStat, SnkStat, RDClk, status

Urgency: Standard

General Description:
If SnkStatClk is not a derivative of RDCLKDiv_GP and is not the same phase as RDCLKDiv_GP, the "SnkStat" input may not be updated properly. (The RStat does not output the correct value based on the SnkStat you have entered.)

Solution

1

This problem occurs because of SnkStat limitations that are dependent on RDCLKDiv_GP.

This issue is fixed in the SPI4.2 v5.2 of the core.

Xilinx strongly recommends that v4.x users of the SPI 4.2 core upgrade to v5.2 or later.

2

If you cannot upgrade to v5.2, you can work around the problem as follows:

Add two additional FD registers to the input of SnkStat and SnkStatClk of PL4 Sink core. The two registers must be clocked by RDClkDiv_GP, which is available from the PL4 Sink core. Two registers are needed to ensure that SnkStat is properly converted to the RDClkDiv_GP domain, as shown in the following diagram:

Work-Around
Work-Around

AR# 15192
Date Created 09/03/2007
Last Updated 03/19/2003
Status Archive
Type ??????