We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 15226

5.1i Timing Analyzer/TRCE/Speed Files - Excessive skew exists between the P and N sides of LVDS and LVPECL outputs


Keywords: speed, LVDS, LVPECL differential, skew, IOB, 1.113, 1.69, Virtex-II Pro, Virtex-II, Pro

Urgency: Standard

General Description:
After I run a timing analysis, the timing report lists the following output path delays for an LVDS pair:

For the P side:
Tiockp = 1.763 ns

For the N side:
Tdiffout + net + Tiodifoi = 2.839 + 0.0 + 1.195 = 4.034

This indicates a skew of 2.271 ns for this differential LVDS signal. Is this correct?


The Virtex-II and Virtex-II Pro speed files were incorrect--the differential pairs and the skew should be very small. To work around this issue, use the P side value as the clock-to-out for both sides.

This problem is fixed in the latest 5.1i Service Pack, available at:
The first service pack containing the fix is 5.1i Service Pack 1.
The first Virtex-II speed file containing the fix is version 1.113
The first Virtex-II Pro speed file containing the fix is version 1.69
AR# 15226
Date Created 07/20/2002
Last Updated 03/06/2005
Status Archive
Type General Article