UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 15228

Virtex-II Pro RocketIO - Why are all GNDA pins in the Virtex-II Pro pin-outs repeated?

Description

Why are all GNDA pins in the Virtex-II Pro pin-outs repeated?

Solution

This is explained in the first footnote on page 4 of the data sheet. You can access the data sheet at: 

http://www.xilinx.com/xlnx/xweb/xil_publications_display.jsp?category=/Data+Sheets/FPGA+Device+Families/Virtex-II+Pro&iLanguageID=1
 

"Two pads on the die are tied to the same package pin (GNDA) in order to lower the resistance on these connections. Thus, duplicate entries exist for GNDA pins."

AR# 15228
Date Created 09/03/2007
Last Updated 05/14/2014
Status Archive
Type General Article