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AR# 15232

5.1i Virtex-II MAP - MAP's Logical DRC flags a nonexistent error regarding FDDRRSE input signals

Description

Keywords: ERROR:LIT:64, FDDRRSE, inputs, tied, logic, level

Urgency: Standard

General Description:
MAP's Logical DRC is incorrectly flagging an error that relates to the input logic to an FDDRRSE:

"ERROR:LIT:64 - FDDRRSE symbol "ldqs_out1/x.x.0_U1" (output signal=ldqs_out1.tri(0)) D inputs are tied to the same logic level. A stable clock signal identical in frequency to the clock signal used to drive the DDR cannot be achieved."

Examination of the logic involved shows that the logic is correct (i.e., the two registers are driven by a signal and its inversion).

Solution

This problem is fixed in the latest 5.1i Service Pack, available at:
http://support.xilinx.com/support/techsup/sw_updates
The first service pack containing the fix is 5.1i Service Pack 3.

Alternatively, you may work around this problem by using the following environment variable to disable the DRC check:

PCs:
set XIL_MAP_SKIP_LOGICAL_DRC=1

Workstations:
setenv XIL_MAP_SKIP_LOGICAL_DRC 1

For more general information about setting ISE environment variables, see (Xilinx Answer 11630).
AR# 15232
Date Created 07/22/2002
Last Updated 09/26/2006
Status Archive
Type General Article