In SPI 4.2 (PL4) core versions 4.0 and 5.0, when I use automatic static alignment (PhaseAlignEn = 1), I observe DIP4 errors on a Sink core. The DIP4 errors occur in the device and may not appear in the simulation.
If DIP4 errors occur, Xilinx recommends that you use fixed static alignment. You can accomplish this by setting the static configuration signal (PhaseAlignEn = 0) located in the "pl4_wrapper" file. You should also set the phase shift value for "rdclk_dcm0" to an appropriate value to successfully capture data. Please see (Xilinx Answer 16112) to determine the optimal phase shift value for your application.
Currently, the automatic static alignment feature is disabled or removed in v5.1 and later versions of SPI-4.2 pending additional verification. Until then, please use fixed static alignment.