UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 15275

Virtex-II Pro PowerPC - How do I access PowerPC's JTAG debug port (BDM) using XMD or SingleStep?

Description

General Description:

How do I access PowerPC's debug port using XMD or SingleStep?

Solution

Depending on the debugging tools, different designs are required in RTL. To use XMD through Xilinx Parallel Cables, the following four ports must be available from the CPU: JTGC405TCK, JTGC405TDI, JTGC405TMS, and C405JTGTDO.

To use SingleStep through WindRiver visionProbe cables, the following six ports must be available from the CPU: JTGC405TCK, JTGC405TDI, JTGC405TMS, C405JTGTDO, JTGC405TRSTNEG, and DBGC405DEBUGHALT.

In Virtex-II Pro devices, the PowerPC JTAG debug ports (including JTGC405TCK, JTGC405TDI, JTGC405TMS, C405JTGTDO, and C405JTGTDOEN) are fully configurable. They can be routed to generic I/O pins or can share FPGA JTAG pins. JTGC405TRSTNEG and DBGC405DEBUGHALT are also configurable, but they cannot be shared with FPGA JTAG pins.

Option 1: Using Generic I/O pins to Access PowerPC JTAG Debug Ports

For XMD:

Bring JTGC405TCK, JTGC405TDI, JTGC405TMS, C405JTGTDO out to user I/O.

For SingleStep:

Bring JTGC405TCK, JTGC405TDI, JTGC405TMS, C405JTGTDO, C405JTGTDOEN, JTGC405TRSTNEG, and DBGC405DEBUGHALT to the top level, and instantiate them with the appropriate I/O buffers. (Be careful to ensure proper signal polarity.) In this case, each PowerPC has dedicated I/O pins and a JTAG chain, and you must select "Single Device" in the SingleStep JTAG and Register settings.

Option 2: Sharing FPGA JTAG Pins

If you want to use an FPGA JTAG pin to access the PowerPC debug port, you MUST connect all PPC JTAG pins into one chain. For example, if there are four PPCs in one Virtex-II Pro device, you must connect all four PPCs into one chain. You CANNOT connect only 1, 2, or 3 PPCs in the chain.

For XMD:

You must instantiate the component "JTAGPPC" in your RTL and connect JTGC405TCK, JTGC405TDI, JTGC405TMS, C405JTGTDO, and C405JTGTDOEN.

For example:

JTAGPPC_i : JTAGPPC port map (

TCK => JTGC405TCK, -- O

TDIPPC => JTGC405TDI, -- O

TMS => JTGC405TMS, -- O

TDOPPC => C405JTGTDO, -- I

TDOTSPPC=> C405JTGTDOEN -- I

);

Since XMD uses iMPACT DLLs, XMD can detect PROMs or other FPGAs on the board.

For SingleStep:

In the RTL, you must instantiate JTAGPPC, and you must connect JTGC405TRSTNEG and DBGC405DEBUGHALT to the generic pins, depending on your board schematic.

Unlike XMD, SingleStep does not detect PROMs or other FPGAs on the board. Consequently, you must select "Multi-device" in the JTAG and Register settings and provide a board file.

For more information, refer to "PowerPC 405 Processor Block Reference Guide" in your EDK kit. This guide includes a chapter that summarizes Virtex-II Pro PPC405 JTAG Debug Port.

AR# 15275
Date Created 09/03/2007
Last Updated 12/15/2012
Status Active
Type General Article