When I use XST to synthesize an HDL design that contains black box cores, I specify the "-read_cores" option to import the EDIF cores for timing analysis and optimization. However, for ChipScope Pro Cores, the following message occurs:
"WARNING:Xst:1474 - Ports for core <icon_pro> do not line up with declaration. Core will not be loaded."
This occurs because of an issue with the CONTROL ports. For XST designs, the CONTROL port is declared in the instantiation templates as a 36-bit output for the ICON Core and a 36-bit input for the ILA Cores. However, bit CONTROL<3> of this bus is actually a status bit that is declared in the opposite direction in the EDIF. This discrepancy is left as it is to simplify the instantiation process; since NGDBuild does not check pin direction, the cores are merged properly during the NGDBuild process.
XST can read in netlists to evaluate the netlist timing. Currently, the netlists associated with the ChipScope Pro Cores cannot be read into XST, but you can avoid the warnings by disabling the "-read_cores" option as follows:
1. Select Synthesize -> Properties.
2. Uncheck the "Read Cores" option under the Synthesis Options tab.
If this option does not appear, select Edit -> Preferences -> Processes. Set the Property Display Level to Advanced to access the advanced options.
This warning might occur with non-ChipScope Pro designs as well. Compare the black box netlist and the instantiation in the HDL to make sure that all port names, bus widths and delimiters, and port directions are identical. Fix any discrepancies to avoid the warning.
The Read Cores option can be disabled to deactivate this processing as well.