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AR# 15354

LogiCORE SPI-4.2 (POS-PHY L4) v5.0 - SrcStat and SrcStatChValid display "X" because the SimPrim model for block RAM becomes unknown when input CLKB is "Low"


Urgency: Hot

General Description:

NOTE: The following information only applies to ISE 4.2i and VHDL simulation. If you are using ISE 5.1i or later, you do not need the tactical patch provided in this Answer record.

When I run post-NGDBuild or post-route simulation with a PL4 core, the Source status signals on the core user interface do not behave properly. Glitches of "x" or "unknown" appear on the SrcStatCh signal, and the SrcStat output is never updated.

When I examine the hierarchy of the Source core, I see that at the beginning of a simulation, the output of a BUFGMUX is "Low" for a short period of time. If the BUFGMUX drives a clock on a block RAM, the outputs of the block RAM become "X" and the contents of the block RAM become corrupted.


This problem is caused by a bug in VHDL SimPrim and UniSim models, and is only observed in the PL4 v5.0 core and the PL4 to 10-Gig Bit Ethernet MAC (XGMII) Bridge core.

If you are a PL4 customer, a tactical patch is available to fix this simulation problem. You may download the patch from the PL4 site in conjunction with PL4 v5.0 core, which is available in 42_ip_update3 at:


If you are a PL4 - XGMII Bridge customer, you may download the patch from the PL4 to XGMII Bridge site.

If you are not a PL4 or a Bridge customer, but have a similar issue when simulating your design with BRAM, please contact Xilinx Customer Support at the nearest location (listed below) and mention this Answer Record (number 15354).

Patch Installation

NOTE: This patch should only be used with the 4.2i Service Pack 3 software.

To install the patch, follow these steps:

1. Unzip the "cr157340_vhdl_BRAM_patch.zip" file into a temporary directory.

2. Compile unisim_VITAL.vhd (contained in the patch) into the Xilinx UniSim simulation library. In ModelSim, use the following command at the command line:

vcom -87 -work unisim unisim_VITAL.vhd

NOTE: For PL4 designs, RTL simulation is not available at this time, so the following step is not necessary. However, if you are simulating a non-PL4 design in RTL simulation, you must compile unisim_VITAL.vhd.

3. Compile simprim_VITAL.vhd (contained in the patch) into the Xilinx SimPrim simulation library. For ModelSim, use the following command:

vcom -87 -work simprim simprim_VITAL.vhd

Who do I Contact for Support?

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E-mail: jhotline@xilinx.com

This issue is fixed in the 5.1i and later software.

AR# 15354
Date Created 09/03/2007
Last Updated 05/03/2010
Status Archive
Type General Article