How should I handle unused pins for the XC9500 family devices? What is their state before and during configuration?
Xilinx recommends tying any unused pins to either the board ground or to a board trace. This will help reduce problems associated with ground bounce and noise. Failure to do so will not harm the device.
Xilinx design tools has a "Create Programmable Ground Pins" option in the Fitting properties. If this option is selected in addition to tying the unused pins to ground, it will be more beneficial regarding noise and ground bounce issues, as these pins will be connected to a ground in the CPLD.
XC9500 5V CPLD:
Unused I/O pins in the XC9500 devices are floating unless an entire function block is empty; then, there is a pull-up on every I/O in that function block. This is also the case before and during configuration.
If you select the "Create Programmable Ground Pins" option in the software, all unused I/O pins will be internally grounded.
9500XL/XV 3.3V/2.5V CPLD:
Unused I/O pins in a completely unused function block are floating with a weak pull-up. This is also the case before and during configuration.
Unused I/O pins in a used function block have the bus-hold circuit enabled (this can be disabled in the design tools).
For more information on the bus-hold logic, see (Xilinx Answer 5175) you select the "Create Programmable Ground Pins" option in the design tools, all unused I/O pins will be internally grounded.
For other common CPLD questions, see the CPLD Tech Tips FAQ: (Xilinx Answer 24167)