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AR# 15394

LogiCORE SPI-4.2 (POS-PHY L4) v4.x - "ERROR: TDAT bus error received incorrect EOP 10" is reported when I simulate a PL4 v4.0 in NC-Verilog


Keywords: POS, PHY, level, 4, CORE Generator, COREGen, error, simulation, tdat, bus, NC-Verilog, EOP 10

Urgency: Standard

General Description:
When I simulate a SPI 4.2 (POS PHY L4) Core v4.0 in NC-Verilog, the following error is reported:

"ERROR: TDAT bus error received incorrect EOP 10."



This issue is fixed in v5.2 of the SPI4.2 (PL4) core.

Xilinx strongly recommends that version 4.x users upgrade the core to version 5.2 or later.


If you cannot upgrade the core to version 5.2, edit the "pl4_monitor.v" file as follows:

Change line 240, "input data_index", so that it reads "input [31:0] data_index".

AR# 15394
Date Created 09/03/2007
Last Updated 03/19/2003
Status Archive