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AR# 15395

LogiCORE SPI-4.2 (POS-PHY L4) v5.0 - Migrating from v4.0 to v5.0 (Migration Guide)

Description

General Description:

This Answer record describes the changes necessary to migrate from v4.0 to v5.0 of the SPI-4.2 core. While every attempt was made to keep constraints and input and output signals as consistent as possible between versions, certain modifications are required to update the constraints and the wrapper file when migrating from v4.0 to v5.0.

Solution

- Because additional signals were added to the PL4 core, the v5.0 wrapper file must be used -- the v4.0 wrapper file does not work. The wrapper file was changed to efficiently implement flow control and add support for up to 256 channels.

- The v5.0 NCF files (pl4_snk_top.ncf and pl4_src_top.ncf) replace the v4.0 NCF files.

- The UCF file must be updated using either Option A or Option B below.

Option A

Replace all PL4 constraints in the UCF file with the PL4 constraints from the CORE Generator. (Use the v5.0 UCF files instead of the v4.0 UCF files.)

Option B

Follow the instructions below to migrate the existing PL4 UCF constraints so they are compatible with v5.0:

Sink Constraints

NOTE: The following Sink constraints apply to the Static Alignment version of the PL4 Core. The Dynamic Alignment constraints require similar modification.

Clocking

A level of hierarchy (StaticAlign_StaticAlign) must be added to all clock constraints. This applies to the following:

rdclk_dcm0

rdclk0_bufg0

snkclk_bufg0

rdclk180_bufg0 (if using CLK0/CLK180)

For example:

INST "pl4_snk_top0/pl4_snk_clk0/rdclk_dcm0" LOC = DCM_X#Y#;

is changed to

INST "pl4_snk_top0/pl4_snk_clk0/StaticAlign_StaticAlign.rdclk_dcm0" LOC = DCM_X#Y#;

The same hierarchy must also be added to the phase shift of the DCM. Note the slight modification to the DCM phase shift value. While this value depends on your board and system, it provides a reasonable starting point, assuming that well-matched traces exist and that RDClk and RDat are edge-aligned.

For example:

INST "pl4_snk_top0/pl4_snk_clk0/rdclk_dcm0" CLKOUT_PHASE_SHIFT = VARIABLE;

INST "pl4_snk_top0/pl4_snk_clk0/rdclk_dcm0" PHASE_SHIFT = 64;

is changed to

INST "pl4_snk_top0/pl4_snk_clk0/StaticAlign_StaticAlign.rdclk_dcm0" CLKOUT_PHASE_SHIFT = VARIABLE;

INST "pl4_snk_top0/pl4_snk_clk0/StaticAlign_StaticAlign.rdclk_dcm0" PHASE_SHIFT = 62;

Area Constraints

Refer to the area constraints in the v5.0 UCF file provided and update them as required.

Block RAM Placements

The hierarchical path of the block RAMs has changed; in addition to using one more block RAM, the v5.0 constraints replace the v4.0 block RAM values.

For example:

INST

"pl4_snk_top0/pl4_snk_core0/pl4_snk_fifo0/pl4_generic_fifo0/generic_fifo_ram0/RamGen36_RamGen36.GenRAM36.GenRAM36.#_BlockRAM36" LOC = "RAMB16_X#Y#" ;

is changed to

INST "pl4_snk_top0/pl4_snk_core0/pl4_snk_sfifo0/pl4_sfifo_top0/generic_fifo_ram0/BlockRAMgen_BlockRAMgen.RamGen36_RamGen36.GenRAM36.GenRAM36.#.BlockRAM36" LOC = "RAMB16_X#Y#" ;

Also, you must add the extra constraint for the additional block RAM as follows:

INST

"pl4_snk_top0/pl4_snk_core0/pl4_snk_sfifo0/pl4_sfifo_top0/generic_fifo_ram0/BlockRAMgen_BlockRAMgen.RamGen36_RamGen36.GenRAM36.GenRAM36.3.BlockRAM36" LOC = "RAMB16_X#Y#" ;

Update the Calendar RAM as follows:

INST "pl4_snk_top0/pl4_snk_core0/pl4_snk_cal0/mem_mem_CalRAM/bmblk_bmblk_BlockRam" LOC = "RAMB16_X#Y#" ;

is changed to

INST "pl4_snk_top0/pl4_snk_core0/c1_c1.pl4_snk_cal0/mem_mem.CalRAM/BlockRam" LOC = "RAMB16_X#Y#" ;

I/O RPMs

NOTE: The following Sink I/O constraints apply to only the Static Alignment version of the PL4 Core.

The Sink I/O RPM location hierarchy should be changed as follows (the "_" changes to a "."):

INST "pl4_snk_top0/pl4_snk_io0/SnkTDat_gen.SnkTDat_gen.3_SnkTDat_Mux" RLOC_ORIGIN=X#Y# ;

is changed to

INST "pl4_snk_top0/pl4_snk_io0/SnkTDat_gen.SnkTDat_gen.3.SnkTDat_Mux" RLOC_ORIGIN=X#Y# ;

The DDR flip-flop I/O placement changes as follows (NOTE: This change is required for all five DDR flip-flop constraints):

INST "pl4_snk_top0/pl4_snk_clk0/pl4_snk_dcm_ctlr0/gen_ddr_dr1" U_SET = pl4_snk_dcm_dr1;

is changed to

INST "pl4_snk_top0/pl4_snk_clk0/StaticAlign_StaticAlign.pl4_snk_dcm_ctlr0/gen_ddr_dr1" U_SET = pl4_snk_dcm_dr1;

Source Constraints

Clocking

Add the following constraint if it does not already exist (where "#" = 1/4 rate of SysClk_P):

NET "TSClk_GP" TNM_NET = "TSClk_GP";

TIMESPEC "TS_TSClk_GP" = PERIOD "TSClk_GP" # MHz HIGH 50% ;

Area Constraints

Refer to the area constraints in the v5.0 UCF file provided and update them as required.

Block RAM Placements

The hierarchical path of the block RAMs has changed, as illustrated in the following example:

NOTE: This must be repeated for all source side block RAMs.

INST "pl4_src_top0/pl4_src_core0/pl4_src_fifo0/PL4_FIFO/generic_fifo_ram0/RamGen36_RamGen36.GenRAM36.GenRAM36.#_BlockRAM36" LOC = "RAMB16_X#Y#" ;

is changed to

INST "pl4_src_top0/pl4_src_core0/pl4_src_fifo0/PL4_FIFO/generic_fifo_ram0/BlockRAMgen_BlockRAMgen.RamGen36_RamGen36.GenRAM36.GenRAM36.#.BlockRAM36" LOC = "RAMB16_X#Y#" ;

Update the Calendar RAM as follows:

INST "pl4_src_top0/pl4_src_core0/pl4_src_cal0/crtram_crtram_cram/bmblk_bmblk_BlockRam" LOC = "RAMB16_X#Y#" ;

is changed to

INST "pl4_src_top0/pl4_src_core0/c1_c1.pl4_src_cal0/crtram_crtram.cram/BlockRam" LOC = "RAMB16_X#Y#" ;

I/O RPMs

The Source I/O RPM location hierarchy should be changed as follows (the "_" changes to a "."):

INST "pl4_src_top0/pl4_src_io0/src_rdy.src_rdy.2.rdy_hi_rdy_hi_src_rdy_hi" RLOC_ORIGIN=X#Y#;

is changed to

INST "pl4_src_top0/pl4_src_io0/src_rdy.src_rdy.2.rdy_hi_rdy_hi.src_rdy_hi" RLOC_ORIGIN=X#Y#;

AR# 15395
Date Created 09/03/2007
Last Updated 05/03/2010
Status Archive
Type General Article