NOTE: This answer record applies to 4.2i software with Service Pack 3 only when PL4 dynamic alignment is being used. This Answer Record does not apply if you are using 5.1i software or PL4 static alignment.
When I simulate my design with a PL4 Sink configured in dynamic alignment mode, back-annotated simulation does not work properly. The following problems are occurring:
- RDCLKDIV_GP = RDCLK_GP should be RDCLKDIV_GP = RDCLK_GP/2
- SnkClk = RDCLK_GP should be SnkClk = RDCLK_GP/2
- The Source side enters the In frame properly (SrcOof becomes "0" after a period of time), but the Sink side is always out of frame (SnkOof always = "1"). As a result, the RStat bus is always "11". This causes the demo testbench to continually send training for the entire simulation.
- No errors occur, but no data is sent across the bus.
When dynamic alignment is used, you must manually open any user-created back-annotated netlist (output of NGD2VHDL or NGD2VER), and add the following parameters that appear below in bold text:
pl4_snk_clk0_DynamicAlign_DynamicAlign_rdclk_dcm0 : X_DCM
CLKIN_DIVIDE_BY_2 => true,
DLL_FREQUENCY_MODE => "HIGH",
CLK_FEEDBACK => "1X",
CLKOUT_PHASE_SHIFT => "NONE",
PHASE_SHIFT => 0
port map (
CLK90 => NLW_pl4_snk_clk0_DynamicAlign_DynamicAlign_rdclk_dcm0_CLK90_UNCONNECTED,
defparam \pl4_snk_clk0/DynamicAlign_DynamicAlign.rdclk_dcm0 .CLKIN_DIVIDE_BY_2 = "TRUE";
defparam \pl4_snk_clk0/DynamicAlign_DynamicAlign.rdclk_dcm0 .DLL_FREQUENCY_MODE = "HIGH";
defparam \pl4_snk_clk0/DynamicAlign_DynamicAlign.rdclk_dcm0 .CLK_FEEDBACK = "1X";
defparam \pl4_snk_clk0/DynamicAlign_DynamicAlign.rdclk_dcm0 .CLKOUT_PHASE_SHIFT = "NONE";
defparam \pl4_snk_clk0/DynamicAlign_DynamicAlign.rdclk_dcm0 .PHASE_SHIFT = 0;
X_DCM \pl4_snk_clk0/DynamicAlign_DynamicAlign.rdclk_dcm0 (
The changes above are only required for back-annotated netlists that you have created using NGD2VER or NGD2VHDL. If you run the implement script in component_name/implement/ and perform back-annotation on the resulting post-PAR files, or perform back-annotation on a design that incorporates the PL4 Core, you will need to make the changes described in this Answer Record.
This is an NGD2VER or NGD2VHDL issue and it is fixed in ISE 5.1i or later.