We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 15438

5.1i Timing Analyzer - Timing Analyzer does not report the correct FF name for a FROM:TO constraint


General Description:

When I run the "Analyze Against User Defined Endpoints" process in Timing Analyzer and select only flip-flops as my source and destination, an incorrect flip-flop name is reported.


This occurs when the data path to both of these flip-flops is the same and the clock path for both flip-flops is the same. Because of this, timing tools select only one of the flip-flops in the SLICE. This can be confusing, as a user may not know that these flip-flops are in the same SLICE during analysis.

This problem is due to a bug in the software; however, it is a reporting problem only -- the timing analysis of the paths to each of the flip-flops is correct.

This will be fixed in the next major software release (after 5.2i).

AR# 15438
Date Created 09/03/2007
Last Updated 01/18/2010
Status Archive
Type General Article