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AR# 15454

LogiCORE SPI-4.2 (POS-PHY L4) v5.0 - "ERROR:MapLib:32..." is reported when I run MAP with the PL4 core

Description

General Description

When I run the Xilinx implementation tools, a MAP application reports the following errors:

"ERROR:MapLib:32 - INV symbol

"spa_a_spi/pl4_snk_top0/pl4_snk_core0/c1_c1.pl4_snk_cal0/N_248_i" (output signal=spa_a_spi/pl4_snk_top0/pl4_snk_core0/c1_c1.pl4_snk_cal0/N_248_i) has an equation that uses an input pin connected to a trimmed signal. Make sure that all the pins used in the equation for this LUT have signals that are not trimmed (see trim report for details on which signals were trimmed)."

"ERROR:MapLib:32 - LUT3 symbol

"spa_a_spi/pl4_snk_top0/pl4_snk_core0/c1_c1.pl4_snk_cal0/cal_eq_1.un1_snkcalendar_len_465" (output signal=spa_a_spi/pl4_snk_top0/pl4_snk_core0/c1_c1.pl4_snk_cal0/un1_snkcalendar_len_465) has an equation that uses an input pin connected to a trimmed signal. Make sure that all the pins used in the equation for this LUT have signals that are not trimmed (see trim report for details on which signals were trimmed)."

Solution

This problem occurs when the PL4 v5.0 netlist is used with the v4.0 wrapper file. If you have migrated from v4.0 to v5.0, you must use the v5.0 wrapper file generated by CORE Generator.

Please see (Xilinx Answer 15395) for additional changes that are necessary when migrating from PL4 v4.0 to v5.0. For a given version of SPI-4.2 core, make sure that you are using the correct version of wrapper, UCF, and EDIF files.

AR# 15454
Date Created 09/03/2007
Last Updated 05/03/2010
Status Archive
Type General Article