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AR# 15492

14.x XPA - General tips on reducing VCD file size using ModelSim

Description

If a timing simulation is run for a long time, VCD files can grow large; file sizes in excess of 1GB are not uncommon. Although Xilinx is investigating solutions that will reduce the size of simulation files, the use of VCD files is currently the easiest and most universal way of providing simulation data to XPower.

The following hints and tips are presented to help you reduce these file sizes.

Solution

The key to reducing the file size is to understand what is being written to the VCD file. For each logic change on a signal that is added to the "monitor list" (using the command "VCD add"), information will be written to a VCD file. Accordingly, VCD file size can be reduced in two ways: reducing the number of signals, and reducing the overall number of logic changes.

Reducing the number of signals:

Do not use the "-r" switch in ModelSim. (The 5.1i documentation erroneously states that this switch should be used.) In fact, the "-r" switch merely increases the size of the VCD file without giving any extra information to XPower. Not using this switch is the simplest way to reduce the size and increase the speed of your simulation.

Reducing the simulation time:

  • Simulate only for the required time (i.e., do not run the simulation any longer than needed).
  • Simulate recursive signals for only as long needed (e.g., simulate a clock for one period).

You can only use the "VCD add" command at the beginning of the VCD file. Therefore, you cannot simulate most signals in your design for 99% of the simulation and add your clock for the last cycle. However, it is possible to work around this: XPower will allow you to add multiple VCD files that will not overwrite (non-conflicting) previous VCD data. You can therefore make one VCD file for your clock, another for a counter, and another for the rest of your design, as follows:

For example, suppose you are working with a simulation that:

  • Will run for 50 ns.
  • Has a clock period of 5 ns.
  • Contains a two-bit counter.
  • Contains other random signals.

Therefore:

  • The 2-bit counter has four states, so it must be simulated for 4 x 5 ns = 20 ns.
  • The clock must be simulated for 1 period -> 5 ns.
  • The random signals must be simulated for the entire simulation.

In the ModelSim window, compile the design and load it normally. Then add the following:

vcd files clock.vcd counter_signals.vcd other_signals.vcd //Creates three VCD files

vcd add -file other_signals.vcd uut/signala //

vcd add -file other_signals.vcd uut/signalb //Adds any other signals in your testbench that will not be added into the other VCD files

run 30 ns

vcd add -file counter_signals.vcd uut/count* //Adds all the counter signals (they begin with the name count)

run 15 ns

vcd add -file clock_signals.vcd uut/clk //Adds the clock signals

run 5 ns

quit -f

Notice the order in which the signals are added: the clock is added only for the last period. If the clock is added in the first period, you must prevent transitions from being added to the VCD file in order to gain the benefits of reduced VCD file size. This is done using the "VCD off" command. (For more information, please refer to the ModelSim command reference.)

The benefits of this process are:

  • A reduced overall VCD file size.
  • A faster simulation time.

The drawbacks are:

  • An in-depth knowledge of the design is required (i.e., Which signals are recursive? What is their period?, etc.).
  • Extra time is needed to prepare the DO/TCL file for ModelSim.
  • A lack of knowledge about the design could lead to too short a simulation time, which will cause incorrect activity information to be passed on to XPower.
AR# 15492
Date Created 09/03/2007
Last Updated 12/19/2012
Status Active
Type General Article
Tools
  • ISE Design Suite - 11
  • ISE Design Suite - 12
  • ISE Design Suite - 13
  • ISE Design Suite - 14